AtlasLAr Calorimeter Notes


Calorimeter Layout

LAr1LAr2
Fig 1: LAr Calo Layout


Calo Cells
Fig 2: Individual cell layout

Hardware

Readout with FEB's (Front End Boards)

FEB Layout
Fig 3: FEB Layout

Note: info given here is based on Columbia U. FEB note [pdf].

Logic Chain

  1. Readout.

  2. Preamplifier: amplification. Depending on its amplitude, the signal amplified with 3 fixed gains (High=100,  Medium=10, Low=1).

  3. Bipolar Shaper: Shaping.

  4. SCA (analog): Sampling at 40 MHz and storage

  5. Gain Selector: Digitization by 12-bit ADC. ADC digitization happens after the SCA controller receives Level 1 (L1) trigger accept.

    During calibration DAC, delay and pattern are loaded via SPAC protocol onto the TTCRx chip. Pattern in this case is the set of calibration lines to be turned on.  Each pattern is a set of 128 bits (four 32 bit words). See also item 10

  6. SCA Controller: performs the address bookkeeping. Keeps track of the Bunch Crossing number and SCA addresses.
  7. TTCRx: The 40 MHz TTCRx output clocks are fanned out to operate various FEB components.  In addition, it transmits the L1 accept, Bunch Counter Reset (BCR), and Event Counter Reset (ECR) signals to the SCA Controllers.

  8. SPAC Slave: part of TTCRx which allows it to be externally configured and reset.

    During calibration DAC, delay and pattern are loaded via SPAC protocol onto the TTCRx chip.

    Pattern is the set of calibration lines to be turned on.  Each pattern is a set of 128 bits (four 32 bit words). See also item 10.

    ¶ DAC is chosen between 0 and 65535.

    ¶ Delay value range for 2004 Test Beam was 0-24 counts with 1.04 ns steps, which allowed to scan the shaped pulse every 1.04 ns.

  9. Read-Out Driver (ROD): Transmission of digitized signals to off-detector via 1.6 GHz optical link.

  10. Summing board: sums 4 channels, thus forming 32 sums or words (4x32 = 128 chan) which are sent to the Tower Builder to form an L1 trigger tower (Fig. 1)

Design Characteristics


DanielGoldin
Last modified: Thu May 4 16:55:00 CDT 2006